AMD has unveiled a new family of mid-range field-programmable gate arrays (FPGAs), adding integrated LPDDR memory controllers, PCIe Gen4 connectivity and updated security features aimed at data-heavy embedded systems.

The Kintex UltraScale+ Gen 2 range targets equipment makers and design teams in medical, industrial automation, test and measurement, and broadcast-markets that often combine fast sensor inputs, strict latency requirements and long product lifecycles.

FPGAs are reprogrammable chips used to implement custom logic in hardware, sitting between general-purpose processors and fixed-function chips. System designers often choose them for tasks such as real-time processing, signal handling and interfacing with specialised I/O.

AMD said the new devices modernise memory subsystems, I/O and security compared with earlier Kintex generations. It also positioned the family as an option for designs that need more bandwidth and connectivity without moving to higher-priced device classes.

Memory and I/O

A key change is the addition of hard memory controllers for LPDDR4X, LPDDR5 and LPDDR5X. Hard controllers are built into the silicon rather than implemented in programmable logic, which can reduce design complexity and improve timing and latency predictability.

PCIe Gen4 support and high-speed transceivers are also new. In broadcast and media workflows, these interfaces are commonly used for capture cards, high-bandwidth video movement and transport across IP networks in live production.

AMD highlighted several use cases: dense 4K and 8K processing pipelines in professional media; pattern generation and data capture in test and measurement; and scalable sensor connectivity for machine vision and control systems in industrial and medical imaging.

Performance claims

AMD said the family delivers up to a 5X increase in memory bandwidth compared with the prior Kintex UltraScale+ generation. This comparison is based on AMD engineering projections for devices expected to include six 32-bit hard LPDDR controllers running at 4,266 Mb/s, versus a previous-generation device using a single 64-bit DDR4 soft controller at 2,666 Mb/s.

It also claimed up to 2X higher channel density per PCIe interface. That claim is based on projected port counts over a PCIe Gen4x8 link and a hard 100 GbE Ethernet interface, compared with an Altera Agilex A5EC065A device with PCIe Gen4x4 and 25 GbE.

Against “competing platforms”, AMD said the family offers up to 80% higher embedded RAM and 2X DSP density, alongside higher LPDDR memory bandwidth. These figures are also based on engineering projections versus published specifications for certain Altera Agilex parts.

Such comparisons matter for OEMs building platforms with tight power and space constraints. More embedded memory and signal-processing resources can reduce the number of external devices needed on a board, while interface density can affect how many input channels or video streams fit within a given form factor.

Security and lifecycle

AMD emphasised security features aimed at systems deployed across distributed networks and regulated environments, including authenticated device operation, bitstream encryption, anti-cloning protections and secure key management. It also referenced CNSA 2.0-grade cryptography.

Long-term supply is another theme for industrial, medical and broadcast equipment makers, where certification cycles and service commitments often extend for many years. AMD said it expects planned availability for the family through at least 2045.

Development continuity remains tied to AMD’s existing FPGA toolchain, with support for Vivado and Vitis. AMD also referenced its portfolio of video, Ethernet and connectivity IP for teams building systems around standard interfaces.

Roadmap and migration

AMD set out a staged rollout for tools, silicon and evaluation hardware. Simulation support for Vivado and Vitis is scheduled for Q3 2026. Pre-production XC2KU050P silicon is scheduled to sample in Q4, and an evaluation kit based on the XC2KU050 and production silicon is also set to start sampling in Q4 2026.

For teams that want to start earlier, AMD described a migration path from the Spartan UltraScale+ family, starting designs with the XCSU200P in the SBVF900 package and later migrating to Kintex UltraScale+ Gen 2 parts in Q4 2026.

AMD said the family is intended for next-generation systems in markets where bandwidth, timing precision and connectivity demands continue to rise.