{"id":24998,"date":"2025-07-27T02:50:12","date_gmt":"2025-07-27T02:50:12","guid":{"rendered":"https:\/\/www.newsbeep.com\/au\/24998\/"},"modified":"2025-07-27T02:50:12","modified_gmt":"2025-07-27T02:50:12","slug":"raja-koduris-mission-to-deliver-high-bandwidth-memory-for-gpus-has-taken-a-turn-that-could-enable-4tb-of-vram-on-ai-cards-joins-sandisk-to-advise-on-ssd-tech-that-could-feed-ai-accelerators","status":"publish","type":"post","link":"https:\/\/www.newsbeep.com\/au\/24998\/","title":{"rendered":"Raja Koduri’s mission to deliver high bandwidth memory for GPUs has taken a turn that could enable 4TB of VRAM on AI cards \u2014 joins Sandisk to advise on SSD tech that could feed AI accelerators"},"content":{"rendered":"

Raja Koduri continues to push his high bandwidth vision for computing, but this time it’s flash, namely HBF (High-Bandwidth Flash) from Sandisk. On Wednesday, the former graphics architect at S3, Apple, AMD (twice), and Intel, announced that he had joined Sandisk\u2019s HBF Technical Advisory Board to guide development and strategy for High-Bandwidth Flash memory technology. Sandisk also shared a press release<\/a> confirming Koduri\u2019s new role, as well as the appointment of Professor David Patterson to the board.<\/p>\n

Excited to partner with Sandisk.When we began HBM development our focus was improving bandwidth\/watt and bandwidth\/mm^2 (both important constraints for mobile), while maintaining competitive capacity with the incumbent solutions. With HBF the focus is to increase memory\u2026July 24, 2025<\/a><\/p>\n

In case you missed it, Sandisk outlined its newest flash memory innovation back in February this year. Dubbed HBF, the key feature of this flash would be the enabling of GPU packing up to 4TB of VRAM<\/a> \u2013 with more to come in future revisions.<\/p>\n

Of course, this isn\u2019t for enthusiasts (yet), but the proponents of HBF want to unleash this huge memory pool attached to a GPU for AI inference workloads. When it was announced, we learned that HBF would weave its magic using multiple high-capacity, high-performance flash core dies, interconnected using through-silicon vias (TSVs), on top of a logic die that can access flash arrays (or rather flash sub-arrays) in parallel. Thus, it would \u201cdeliver 8-16X [VRAM] capacity at similar cost.\u201d It relies on BICS 3D NAND using the CMOS directly bonded to Array (CBA) design that bonds a 3D NAND memory array on top of an I\/O die made using logic process technology.<\/p>\n

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Back to Koduri\u2019s announcement, via social media, and the erstwhile GPU architect contrasted the development focus of HBM and HBF. The former targeted bandwidth\/watt and bandwidth\/mm^2. Meanwhile, \u201cWith HBF the focus is to increase memory capacity (per-$, per-watt and per-mm^2) significantly while delivering competitive bandwidth,\u201d explained Koduri. This will provide a significant boost to both AI training and inference, he indicated, going so far as claiming HBF could \u201crevolutionize edge AI.\u201d<\/p>\n

Sandisk\u2019s press release confirmed that, in their high-level roles, Koduri and Prof Patterson<\/a> would help \u201cprovide strategic guidance, technical insight, market perspective, and shape open standards as Sandisk prepares to launch HBF.\u201d We don’t have a clear timescale for the launch of HBF, as yet.<\/p>\n

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