Alibaba has revealed a new server chip that it says is the most powerful processor ever to use the RISC-V instruction set.<\/p>\n
According to a social media post<\/a> by Alibaba\u2019s DAMO Academy, which develops some of its chips, the new XuanTie C950 is ready to power cloudy servers, generative AI workloads, high-end robotics, and edge computing devices.<\/p>\n \u201cThe XuanTie C950 is equipped with a self-developed AI acceleration engine, and for the first time natively supports large models with hundreds of billions of parameters, such as Qwen3 and DeepSeek V3, potentially becoming a new type of high-end CPU for the AI Agent era,\u201d the post enthuses.<\/p>\n Alibaba claims the machine\u2019s single-core general-purpose performance \u201cexceeded 70 points in the SPECint 2006 benchmark test.\u201d Photos from Tuesday event at which Alibaba announced the chip suggest its SPECInt 2017 benchmark result is 2.6GHz. Per analysis<\/a> by Google researcher Laurie Kirk puts it nearly on par with Apple\u2019s M1 chip \u2013 which the iGiant launched in the year 2020.<\/p>\n Kirk also noted that Alibaba claimed it\u2019s implemented version 23.1 of the RISC-V RVA, a minor update proposed<\/a> in August 2025. She expressed surprise Alibaba was able to use it so quickly.<\/p>\n A product page<\/a> and spec sheet<\/a> for the chip add more details \u2013 but also omit details like core count and instead offer the non-specific description of the chip as a \u201c64-bit multi-core CPU IP.\u201d<\/p>\n Based on those documents the \u201cacceleration engine\u201d mentioned above is probably the XuanTie Tensor Processing Engine (TPE) and supports data types from FP16 down to INT4\/FP8, plus the micro-scaling formats MXFP8, MXFP4, and RVFP4. The chip can achieve 8 TOPS per TPE.<\/p>\n The memory subsystem apparently \u201ccomprises a high-performance multi-level cache hierarchy with an ultralow 4-cycle load-to-use L1 data cache latency, a private per-core L2 cache supporting large capacity configurations, and an MMU with multiple RISC-V virtual memory modes and two-stage address translation.\u201d<\/p>\n In a section of the spec sheet discussing buses, there\u2019s a mention of a multi-processor mode that \u201cleverages the XL-300 interconnect to form clusters of up to 8 cores.\u201d<\/p>\n Posts The Register has seen suggest Alibaba had the chip made using a 5nm process, a feat that\u2019s not beyond some Chinese chipmakers. Whether they can build chips of that caliber in large quantities is less certain.<\/p>\n