{"id":389520,"date":"2026-04-09T08:35:11","date_gmt":"2026-04-09T08:35:11","guid":{"rendered":"https:\/\/www.newsbeep.com\/ie\/389520\/"},"modified":"2026-04-09T08:35:11","modified_gmt":"2026-04-09T08:35:11","slug":"redefining-ai-inference-with-new-silicon-architecture","status":"publish","type":"post","link":"https:\/\/www.newsbeep.com\/ie\/389520\/","title":{"rendered":"Redefining AI Inference With New Silicon Architecture"},"content":{"rendered":"

\t\t\t\t\tLow Power-High Performance<\/a><\/p>\n

SPONSOR BLOG<\/p>\n

Validating an optimized data movement architecture that ensures arithmetic units receive a steady stream of data every cycle.<\/p>\n

\t\t\t\t\t\t\t\"popularity\"<\/p>\n

AI inference is rapidly becoming the largest and most demanding segment of the AI market, but the cost of running these workloads continues to be a major challenge. VSORA, a fabless semiconductor company, is tackling this problem head-on with a fresh approach to high\u2011performance AI processing and a deep collaboration with Cadence.<\/p>\n

VSORA develops advanced AI chips that dramatically reduce the cost per query for data centers while enabling powerful edge AI applications. Its Jotunn8 architecture targets hyperscale inference workloads, while the Tyr product family focuses on high\u2011performance edge use cases such as autonomous driving.<\/p>\n

\"\"<\/p>\n

At the heart of VSORA\u2019s innovation is a completely rethought data\u2011movement architecture. By optimizing how data flows through silicon and ensuring arithmetic units receive a steady stream of data every cycle, VSORA achieves significantly higher utilization and processing efficiency than traditional solutions, without compromising on the embedded memory needed for today\u2019s massive neural networks.<\/p>\n

To bring this architecture to life, VSORA relies extensively on Cadence\u2019s end\u2011to\u2011end design and verification ecosystem. Their collaboration spans the full flow, from early architectural simulation to physical implementation, packaging, and board design.<\/p>\n

VSORA uses Cadence Palladium Enterprise Emulation to run long simulations. As it\u2019s available on the cloud, it\u2019s flexible to use when needed. Cadence\u2019s Xcelium Logic Simulation is used for RTL simulation, Genus Synthesis Solution and Innovus Implementation System for physical implementation, Modus for DFT and ATPG, Allegro X Design Platform for PCB design, and the Sigrity X Platform for signal and power integrity simulation. In addition, VSORA also sought help from Cadence\u2019s design services team to build its chip and leverage its expertise in areas such as physical implementation and front-end design.<\/p>\n

This comprehensive toolchain allowed VSORA to simulate and validate the full system, from power management to interposers to power grids, ensuring that their silicon performs reliably in real\u2011world conditions.<\/p>\n

With Jotunn8 heading into deployment and development already underway on its next-generation chips at even more advanced nodes, VSORA\u2019s partnership with Cadence continues to be central to advancing AI inference performance and efficiency. Learn more about how\u00a0VSORA is redefining AI inference with Cadence<\/a>.<\/p>\n

<\/p>\n

\t\t\t\t\t\t\tTanushri Shah \u00a0\u00a0(all posts)<\/a><\/p>\n

<\/p>\n

\t\t\t\t\t\t\tTanushri Shah is a marketing editor at Cadence.<\/p>\n","protected":false},"excerpt":{"rendered":"Low Power-High Performance SPONSOR BLOG Validating an optimized data movement architecture that ensures arithmetic units receive a steady…\n","protected":false},"author":2,"featured_media":389521,"comment_status":"","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[6],"tags":[220,81770,61,16374,60,80,172863],"class_list":{"0":"post-389520","1":"post","2":"type-post","3":"status-publish","4":"format-standard","5":"has-post-thumbnail","7":"category-technology","8":"tag-ai","9":"tag-cadence","10":"tag-ie","11":"tag-inference","12":"tag-ireland","13":"tag-technology","14":"tag-vsora"},"_links":{"self":[{"href":"https:\/\/www.newsbeep.com\/ie\/wp-json\/wp\/v2\/posts\/389520","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.newsbeep.com\/ie\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.newsbeep.com\/ie\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.newsbeep.com\/ie\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/www.newsbeep.com\/ie\/wp-json\/wp\/v2\/comments?post=389520"}],"version-history":[{"count":0,"href":"https:\/\/www.newsbeep.com\/ie\/wp-json\/wp\/v2\/posts\/389520\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.newsbeep.com\/ie\/wp-json\/wp\/v2\/media\/389521"}],"wp:attachment":[{"href":"https:\/\/www.newsbeep.com\/ie\/wp-json\/wp\/v2\/media?parent=389520"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.newsbeep.com\/ie\/wp-json\/wp\/v2\/categories?post=389520"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.newsbeep.com\/ie\/wp-json\/wp\/v2\/tags?post=389520"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}