{"id":152633,"date":"2025-11-25T20:13:20","date_gmt":"2025-11-25T20:13:20","guid":{"rendered":"https:\/\/www.newsbeep.com\/il\/152633\/"},"modified":"2025-11-25T20:13:20","modified_gmt":"2025-11-25T20:13:20","slug":"tsmcs-cowos-packaging-capacity-reportedly-stretched-due-to-ai-demand-intels-emib-and-foveros-eyed-as-potential-solution-to-bottleneck","status":"publish","type":"post","link":"https:\/\/www.newsbeep.com\/il\/152633\/","title":{"rendered":"TSMC’s CoWoS packaging capacity reportedly stretched due to AI demand \u2014 Intel’s EMIB and Foveros eyed as potential solution to bottleneck"},"content":{"rendered":"

TSMC\u2019s dominance in advanced packaging has hit a supply-side wall. With the company’s advanced CoWoS packaging capacity booked out by flagship AI players such as Nvidia, AMD, and Google<\/a>, second-tier ASIC vendors and major U.S. chipmakers are now exploring Intel\u2019s EMIB and Foveros as alternative back-end options. That includes customers manufacturing logic at TSMC’s Arizona facility, but seeking faster, domestic packaging pathways \u2014 something Intel\u2019s Rio Rancho, New Mexico, site is already positioned to offer.<\/p>\n

CoWoS remains technically superior. However, new reports have pointed to Intel picking up packaging interest from firms that are either blocked from accessing CoWoS or looking for a shorter route to production. TrendForce <\/a>in particular notes that Intel has already begun packaging some customer designs originally scoped for TSMC CoWoS, and is seeing growing inbound interest from non-traditional clients as a result.<\/p>\n

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While performance obviously remains a paramount consideration, we\u2019re at an inflection point in AI silicon production, and time-to-package is going to become an increasingly important deciding factor for many chipmakers.<\/p>\n

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Intel\u2019s EMIB (Embedded Multi-die Interconnect Bridge) technology<\/a> connects chiplets using tiny silicon bridges embedded directly in the package substrate, eliminating the need for a large silicon interposer. This reduces both cost and thermal complexity, especially for designs that don\u2019t need the wide I\/O bandwidth or power delivery footprint of full CoWoS. Intel\u2019s Foveros technology, by contrast, vertically stacks dies using through-silicon vias or direct copper bonding. It offers high interconnect density and heterogeneous node integration, at the cost of more stringent thermal and yield considerations.<\/p>\n

TSMC\u2019s CoWoS-L remains the go-to option for high-performance AI GPUs<\/a> and HBM-heavy accelerators. Its capacity, however, is finite. TSMC is planning larger interposer sizes of up to 9.5x reticle by 2027, but that expansion is not arriving fast enough for the industry\u2019s current volume requirements. Nvidia is increasing orders for H200<\/a> and B100 accelerators, both of which require extensive CoWoS packaging and high-stack HBM.<\/p>\n

Intel has confirmed that some customer designs initially scoped for CoWoS have been ported to Foveros without modification. Its New Mexico facility, which handles both EMIB and Foveros packaging, is being scaled up by 30% and 150% respectively. Unlike TSMC<\/a>, Intel\u2019s packaging lines are not yet at saturation, and its U.S. location aligns with recent government funding and client interest in onshore manufacturing.<\/p>\n

EMIB provides enough die-to-die bandwidth for inference accelerators, network ASICs, and other lower-bandwidth workloads, while sidestepping CoWoS\u2019s cost and capacity constraints. It also supports integration with HBM via EMIB-T, which adds through-silicon vias (TSVs) for memory stacking without full interposers.<\/p>\n

Hiring for EMIB expertise<\/p>\n

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\"Intel\"\n<\/p>\n

(Image credit: Intel)<\/p>\n

While Intel hasn\u2019t formally named customers, MediaTek and Marvell were identified in recent reporting<\/a> from DigiTimes as evaluating Intel\u2019s packaging for second-tier AI ASICs. Both companies have existing ASIC roadmaps with inference-class acceleration and have previously worked with non-TSMC foundries.<\/p>\n

Qualcomm and Apple have gone further, adding EMIB and Foveros to internal job postings. Apple recently advertised a DRAM Packaging Engineer role listing experience with CoWoS, EMIB, and SoIC as desirable. Qualcomm listed EMIB in a position description focused on advanced server packaging, suggesting that its data center ambitions may involve Intel\u2019s technology. While these listings don\u2019t confirm anything solid, they indicate technical alignment and internal exploration. Broadcom has also been mentioned in several analyst briefings as a prospective client.<\/p>\n

TrendForce cautions that while there\u2019s real interest in EMIB, current evaluation doesn\u2019t necessarily mean that Apple or Qualcomm will ship Intel-packaged products in the near term. Nonetheless, the presence of these companies in packaging-focused hiring pipelines shows a deliberate move to hedge their bets. At a minimum, they are preparing for a supply chain where CoWoS access is no longer guaranteed.<\/p>\n

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A fragmented back-end ecosystem could emerge<\/p>\n

The practical upshot of these moves is a shift toward split front-end\/back-end workflows. Chips fabricated on leading-edge nodes at TSMC\u2019s Fab 21 in Arizona<\/a> may soon be routed directly to Intel\u2019s Rio Rancho site or other U.S.-based packaging facilities, instead of returning to Taiwan for CoWoS.<\/p>\n

This model would introduce complexity, particularly in substrate qualification, die design compatibility, and vendor coordination. Intel claims to have aligned design rules with TSMC and major memory suppliers to support these split flows, though these claims have not yet been tested at scale.<\/p>\n

Amkor, the largest U.S.-based OSAT company, is also part of this equation. Its Arizona site is on track to begin operations in 2028<\/a> and will package wafers from TSMC Arizona for customers, including Apple and Nvidia. Amkor’s role in closing the domestic packaging gap was acknowledged in recent Commerce Department guidance on CHIPS Act implementation last year. For now, Intel\u2019s earlier availability gives it a time-to-market advantage.<\/p>\n

The current imbalance in packaging capacity has created an unusual opening for Intel to expand its foundry presence, not by beating TSMC on performance metrics, but by offering a viable, available alternative. EMIB and Foveros may not dethrone CoWoS in raw performance terms, but they are mature enough to carry AI inference ASICs and modular SoCs through to production without delay.<\/p>\n

That window will not stay open forever. By 2027, if TSMC executes on its CoWoS and SoIC expansion plans, and if Amkor comes online at volume, packaging scarcity could ease. By then, Intel will need to show not only technical parity but also deliver success across customer projects that span logic, memory, and system integration.<\/p>\n

Until then, Intel\u2019s packaging roadmap<\/a> is intersecting with a real market need. The next two years will test whether EMIB and Foveros can do more than catch overflow, and whether Intel\u2019s foundry revival has more than just a fabrication story to tell.<\/p>\n

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