{"id":381975,"date":"2026-04-16T05:34:07","date_gmt":"2026-04-16T05:34:07","guid":{"rendered":"https:\/\/www.newsbeep.com\/nz\/381975\/"},"modified":"2026-04-16T05:34:07","modified_gmt":"2026-04-16T05:34:07","slug":"correcting-and-replacing-panmnesia-to-mass-produce-pcie-6-4-cxl-3-2-fusion-switch","status":"publish","type":"post","link":"https:\/\/www.newsbeep.com\/nz\/381975\/","title":{"rendered":"CORRECTING and REPLACING Panmnesia to Mass-Produce PCIe 6.4-CXL 3.2 Fusion Switch"},"content":{"rendered":"

DAEJEON, South Korea–(BUSINESS WIRE<\/a>)–Please replace the release with the following corrected version due to multiple revisions.<\/p>\n

\nThe updated release reads:\u00a0<\/p>\n

\nPANMNESIA TO MASS-PRODUCE PCIe 6.4-CXL 3.2 FUSION SWITCH<\/p>\n

\nWorld\u2019s Only ASIC Switch Chip with Port-Based Routing (PBR) and Full CXL 3.2 Standard Compliance<\/p>\n

\nPanmnesia (CEO Myoungsoo Jung), a South Korean fabless company developing link solutions for AI infrastructure, announced that it will mass-produce its PCIe 6.4-CXL 3.2 fusion switch* chip in the second half of this year.<\/p>\n

\nThe chip is the world’s only silicon to fully implement the CXL 3.2 specification, including Port-Based Routing** (PBR). Panmnesia first unveiled a sample of the silicon in October last year.<\/p>\n

\n*Switch: A device that serves as an intermediary bridge connecting various system devices such as GPUs and memory<\/p>\n

\n** Port-Based Routing: A routing method that directs signals based on ports assigned to each device, enabling devices to be connected in any desired topology. This stands in contrast to hierarchy-based routing, which is limited to tree topologies, offering significantly greater flexibility in system architecture.<\/p>\n

\n\u25a0 Product Overview<\/p>\n

\nThis chip supports both PCIe and CXL protocols on a single die, enabling connectivity across a wide range of devices that make up modern data centers and HPC environments \u2014 including \u25b2PCIe-based GPUs \u25b2PCIe switches \u25b2CXL CPUs \u25b2CXL memory expanders \u25b2CXL-based AI accelerators.<\/p>\n

\nIn particular, Panmnesia’s PCIe 6.4-CXL 3.2 fusion switch enables composable architecture \u2014 a structure in which diverse system resources are pooled, managed independently, and flexibly allocated based on application demand \u2014 to be implemented at rack\u2020 scale, minimizing resource waste across AI data centers and HPC environments. This translates into reduced capital expenditure (CAPEX) and operating expenditure (OPEX) for systems handling large-scale workloads, including large language models (LLMs), retrieval-augmented generation (RAG), deep learning recommendation models (DLRM), and MPI-based scientific simulations.<\/p>\n

\n\u2020Rack: A unit that consolidates multiple servers into a single enclosure.<\/p>\n

\n\u25a0 Key Differentiators<\/p>\n

\nAs demand for AI grows rapidly, enterprises are operating large numbers of accelerators in parallel to deliver more advanced services powered by large-scale AI models. In this environment, the overall performance of a system depends not only on the compute power of individual accelerators, but equally on how quickly and efficiently they can communicate with others. Panmnesia’s switch maximizes performance per dollar in AI data centers by accelerating this communication through the following differentiating capabilities.<\/p>\n

\n1. World\u2019s Only Port-Based Routing Support<\/p>\n

\nPanmnesia\u2019s switch supports both port-based routing (PBR) and hierarchy-based routing (HBR) on a single chip. Unlike HBR, which limits connectivity to a tree structure centered on the CPU, PBR allows switches and devices to be freely interconnected in any topology. This means data paths between devices can be flexibly designed, shortening data transfer routes and playing a critical role in improving system performance. Furthermore, Panmnesia\u2019s switch chip enables Direct Peer-to-Peer communication on a fabric built with port-based routing, allowing devices to exchange data directly with minimal CPU involvement and maximizing communication efficiency. Panmnesia is currently the only company in the industry to offer a switch chip with port-based routing support.<\/p>\n

\n2. Large-Scale Fabric via Switch Cascading<\/p>\n

\nWith cascading support, multiple switches can be chained together to unify thousands of devices across multiple server racks into a single fabric \u2014 without relying on high-latency networks such as Ethernet.<\/p>\n

\n3. Accelerated Device-to-Device Communication<\/p>\n

\nThe switch supports all CXL sub-protocols\u2014CXL.cache, CXL.mem, and CXL.io\u2014ensuring cache coherency between devices and minimizing unnecessary data copies. It also fully supports PCIe Gen 6 data transfer speeds of 64GT\/s, further enhancing large-scale data movement performance.<\/p>\n

\n4. Proprietary Ultra-Low-Latency Controller<\/p>\n

\nPanmnesia’s switch chip is built on a fully proprietary controller and IP, another key differentiator. Designed and optimized for CXL architectures, the controller achieves double-digit nanosecond (ns) latency, boosting response time and throughput across the switch and overall system. The controller logic can also be freely modified to accommodate customer-specific requirements, enabling expansion into tailored custom solutions.<\/p>\n

\n\u25a0 Availability<\/p>\n

\nPanmnesia\u2019s PCIe 6.4-CXL 3.2 fusion switch silicon is out now and early access partners can request samples and pilot systems. For more information about samples, products, and partnership, please contact sales@panmnesia.com<\/a>.<\/p>\n

\n\u25a0 Appendix: About Panmnesia<\/p>\n

\nPanmnesia is an AI infrastructure company that develops link solutions to make AI data centers more efficient. As part of the solutions, the company has developed PCIe\/CXL controllers and PCIe\/CXL switches, and has introduced hybrid link architectures that integrate interconnect technologies such as UALink and NVLink Fusion, along with advanced interconnect and semiconductor technologies including HBM.<\/p>\n

\nRecognized for its technological leadership, Panmnesia secured approximately USD 60 million in Series A funding in 2024 and achieved a company valuation of approximately USD 250 million.<\/p>\n","protected":false},"excerpt":{"rendered":"DAEJEON, South Korea–(BUSINESS WIRE)–Please replace the release with the following corrected version due to multiple revisions. The updated…\n","protected":false},"author":2,"featured_media":381976,"comment_status":"","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[6],"tags":[111,139,69,145],"class_list":{"0":"post-381975","1":"post","2":"type-post","3":"status-publish","4":"format-standard","5":"has-post-thumbnail","7":"category-technology","8":"tag-new-zealand","9":"tag-newzealand","10":"tag-nz","11":"tag-technology"},"_links":{"self":[{"href":"https:\/\/www.newsbeep.com\/nz\/wp-json\/wp\/v2\/posts\/381975","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.newsbeep.com\/nz\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.newsbeep.com\/nz\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.newsbeep.com\/nz\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/www.newsbeep.com\/nz\/wp-json\/wp\/v2\/comments?post=381975"}],"version-history":[{"count":0,"href":"https:\/\/www.newsbeep.com\/nz\/wp-json\/wp\/v2\/posts\/381975\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.newsbeep.com\/nz\/wp-json\/wp\/v2\/media\/381976"}],"wp:attachment":[{"href":"https:\/\/www.newsbeep.com\/nz\/wp-json\/wp\/v2\/media?parent=381975"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.newsbeep.com\/nz\/wp-json\/wp\/v2\/categories?post=381975"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.newsbeep.com\/nz\/wp-json\/wp\/v2\/tags?post=381975"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}