Interface domains and standards include:<\/p>\n
On-die or SoC fabric: AMBA (Advanced Microcontroller Bus Architecture) AXI (Advanced eXtensible Interface) or CHI (Coherent Hub Interface), coherent and non-coherent network on chips (NoCs)
\nHost-to-device: PCIe (Peripheral Component Interconnect Express)
\nDie-to-die (in-package): UCIe (Universal Chiplet Interconnect Express), BoW (Bunch of Wires), OpenHBI (Open High Bandwidth Interconnect), OIF XSR (Optical Internetworking Forum \u2013 Extra Short Reach), CHI C2C (chiplet to chiplet), AXI C2C protocol over PHY), NVLink-C2C
\nScale-up within rack or pod: Nvidia\u2019s NVLink, UALink, Infinity Fabric
\nScale-out rack-to-rack: Ultra Ethernet (UE) and UET (Transport), InfiniBand, RoCE (Remote Direct Memory Access over Converged Ethernet)
\nMemory pooling or coherent attach: CXL (Compute Express Link)
\nIn-package memory: JEDEC HBM3e or HBM4 (High Bandwidth Memory)
\nPackaging: Silicon interposers or bridges, TSMC\u2019s CoWoS (Chip-on-Wafer-on-Substrate), Intel\u2019s EMIB (Embedded Multi-die Interconnect Bridge) or EMIB-T (with Through-Silicon Vias)
\n3D: Intel\u2019s Foveros, TSMC\u2019s SoIC (System on Integrated Chips)
\nEmerging optical: CPO (Co-Packaged Optics), Optical I\/O (over UCIe streaming)<\/p>\n
While interface terms such as I\/O and interconnect are sometimes used interchangeably, there are distinct differences.<\/p>\n
\u201cInterconnect is what connects to chips at the physical layer,\u201d said Priyank Shukla, director of product management for interface IP at Synopsys<\/a>. \u201cWhen people talk about what interconnect they\u2019re using, PCIe or UALink could be an interconnect technology. But when you say I\/O, the typical understanding is that it\u2019s low-speed and general-purpose. You\u2019re not focusing on a controller or anything else, just the physical input output. Meanwhile, I\/O chiplets take data in or out from the core die.\u201d<\/p>\n With all the interconnect options and specifications, it can be confusing for designers to pick the correct one.<\/p>\n \u201cAs IP providers, we\u2019ve had to explain where each of these protocols fits in,\u201d said Mick Posner, senior product marketing group director for chiplets and IP solutions at Cadence<\/a>. \u201cWe often get the question, \u2018Which one should I choose?\u2019 We have to say, \u2018Please explain what you\u2019re trying to do,\u2019 because there is a bit of overlapping.\u201d<\/p>\n Each interconnect is tailored to a specific purpose, so one cannot replace all. \u201cWhy are you going to sacrifice performance, power, area, and latency for your use case to support a generic interface that\u2019s really not going to differentiate you?\u201d Posner added. \u201cThese vendors don\u2019t want a generic interface.\u201d<\/p>\n Rather than winner-take-all, the industry is converging on a layered approach. \u201cYou can standardize the building blocks and still have different fabrics for on-package communication, in-rack expansion, and rack-scale connectivity, because the constraints are different at each tier,\u201d said Arif Khan, vice president of product management and marketing for the Silicon Solutions Group at Cadence. \u201cThe practical outcome for designers is more choice, but also clearer roles \u2014 one set of links for broad compatibility, another for memory semantics and pooling, and others for ultra-low-latency scale-up domains. The systems that win will be the ones that blend these cleanly.\u201d<\/p>\n More options bring more challenges. \u201cThe proliferation itself is part of the problem,\u201d said Ashish Darbari, CEO of Axiomise<\/a>. \u201cFive years ago, you picked an interconnect, picked a package, and got on with it. Recently, I was talking to an architect and learned that these days it is common for architects to simultaneously evaluate UCIe 2.0 for the compute-to-memory link, BoW for cost-sensitive I\/O, EMIB-T for the high-bandwidth bridge, CHI on the host side, and a non-coherent NoC for the streaming accelerators \u2014 all in the same design. There is a reason for each of them, but the challenge is that no one entity owns everything, and you\u2019re not integrating one protocol. You\u2019re stitching a stack of them. The consequence of this is that bugs will live between the seams of this stack, not necessarily in any one of them.\u201d<\/p>\n A lot of interconnect innovation is focused on achieving amazing performance for a single AI workload. \u201cWe\u2019re seeing networks evolve, and all these technologies, I\/Os, links, and connectivity protocols evolve along with that,\u201d said Saurabh Gayen, chief solutions architect at Baya Systems<\/a>. \u201cIt\u2019s very fast-moving and a lot of things are emerging and fighting for dominance.\u201d<\/p>\n Choosing the right interfaces is about the engineers\u2019 comfort level, along with product definition. \u201cThere might even be hedging of bets. Customers say, \u2018We need something that\u2019s able to support both, because we don\u2019t know what\u2019s going to win,\u2019\u201d said Gayen. \u201cYou have to make your bets now, and a year from now is when your product comes out. If you pick the wrong horse, you\u2019re done. There\u2019s a lot of bottom-up technical assessment, but that\u2019s not the only thing that goes into it. We\u2019ve seen technology win out that might not be technically the best, but it had the momentum behind it. It had the ecosystem coalesce around it. All these top-down and bottom-up considerations are what we\u2019re seeing from our customers.\u201d<\/p>\n In fact, there may be too many choices. \u201cThe real challenge is that the use cases overlap just enough to create confusion, while the implementation costs do not overlap at all,\u201d said Lou Ternullo, senior director of product management for silicon IP at Rambus<\/a>. \u201cIf the design needs ubiquitous compatibility and predictable bring-up, PCIe remains the default choice. If the bottleneck is memory capacity and utilization, CXL becomes compelling because it changes what the fabric can do, not just how fast it moves bits. If the system is a tightly coupled accelerator pod chasing peak bandwidth at very low latency, that is where specialized scale-up interconnects tend to earn their keep. Most modern systems end up mixing these, because one link rarely checks every box.\u201d<\/p>\n In a crowded field, not all standards can hold equal ground. \u201cUCIe, HBI, and high-speed SerDes fabrics are rising in popularity due to disaggregation economics,\u201d said William Wang, CEO of ChipAgents<\/a>. \u201cProprietary die-to-die interfaces are declining as standardization accelerates ecosystem interoperability.\u201d<\/p>\n Andy Nightingale, vice president of product management and marketing at Arteris<\/a>, agreed that bespoke, one-off, die-to-die, and ad-hoc proprietary interfaces are losing favor because they don\u2019t compose well across vendors or product generations. \u201cEvery custom link is a permanent tax on validation, bring-up, and supply-chain optionality,\u201d he said.<\/p>\n The overall trend is for short-reach, high-bandwidth interconnects through die-to-die and 2.5D interposers, or 3D die stacking, said Hee Soo Lee, high-speed digital design segment lead at Keysight EDA<\/a>. \u201cThey deliver extremely wide buses at higher speeds.\u201d<\/p>\n UCIe for chiplets and 3D \u201cStandardized die-to-die and memory-centric interconnects are winning because they reduce ecosystem friction and verification burden,\u201d said Arteris\u2019 Nightingale. \u201cUCIe is explicitly aimed at multi-vendor chiplet interoperability with a defined stack and compliance testing, which is the kind of boring standardization engineers secretly love.\u201d<\/p>\n However, UCIe is yet to have the same dominance in the chiplet space as PCIe has in the board-to-board component interconnect space.<\/p>\n \u201cChiplet-based design, fundamentally, should be exactly the same as chip-to-chip, except now it\u2019s die-to-die,\u201d said Cadence\u2019s Posner. \u201cSo why in the world is it more complex when you take these dies and package them in the same area versus going across chip-to-chip? It really comes down to the die-to-die interfaces. When you\u2019re going from chip to chip, protocols like PCIe make a huge amount of sense because you have a dedicated protocol. Both sides understand it. And we\u2019re in this interim area where multi-die is exploding, but there isn\u2019t a PCIe of die-to-die. Don\u2019t get me wrong, UCIe has come in and is trying to provide that gateway and make a standard that everyone can utilize. But when you\u2019re looking at an application such as the data center, what are you doing? Is this a CPU-to-CPU connection? Is it GPU-to-CPU? Is it GPU-to-CPU to memory?\u201d<\/p>\n Despite the complications, chiplets are here to stay. \u201cOne of the benefits of chiplets is a mix and match,\u201d said Keysight\u2019s Lee. \u201cInstead of having to get everything from integrated IDMs, you can include off-the-shelf components. You can get a chiplet, plug it into your system, and make the entire system work. That speeds up ecosystem adoption.\u201d<\/p>\n PCIe and CXL PCIe is widespread outside of the AI space, as well. \u201cPCIe and Ethernet still dominate applications such as mainstream data centers, enterprise IT, and personal computing,\u201d said Kent Orthner, principal solutions architect at Baya Systems. \u201cThey\u2019re getting faster with a lot of these external protocols. Memories have become faster and faster in recent years, using the HBM in-package memory solution, and that\u2019s moving forward to give super-fast, low-latency access to external memory.\u201d<\/p>\n CXL will always live in a particular use case. \u201cCXL was designed for CPU-to-memory,\u201d said Cadence\u2019s Posner. \u201cIt enables memory sharing and memory pooling. No other protocol does that.\u201d<\/p>\n Arteris\u2019 Nightingale agreed. \u201cCXL continues to pull more of the memory and accelerator attach story toward coherent fabrics and pooled or shared memory models \u2014 handy when AI workloads are dominated by data movement and memory bandwidth, not just raw MACs,\u201d he noted.<\/p>\n The AI data center\/HPC race \u201cNVLink and UALink are getting more traction as the amount of compute and memory within each GPU or accelerator increases and more data needs to be transferred between GPUs,\u201d said Vinci\u2019s Radhakrishnan. \u201cNVLink is the primary protocol for NVIDIA GPU-based systems, while UALink is gaining attention as an open standard for accelerator-to-accelerator communication. Until photonics-based CPO matures, NVLink and UALink are two of the main protocols AI chipmakers are relying on to connect multiple GPUs in parallel and move data efficiently between them.\u201d<\/p>\n Even with these definitions, it\u2019s not always clear which one engineers should choose. \u201cWe often get asked, \u2018Should I be using NVLink Fusion, or should I go with UALink?\u2019\u201d said Cadence\u2019s Posner. \u201cNVLink Fusion is the public version of Nvidia\u2019s NVLink. They\u2019ve extended it because they want people to hook up into their environment, so that\u2019s the CPU-to-GPU connection. UALink is spearheaded by AMD, based on their Infinity fabric, looking for GPU-to-CPU connectivity and GPU-to-GPU, but within their ecosystem. Again, it\u2019s public.\u201d<\/p>\n PCIe used to be the CPU-to-accelerator interface of choice. \u201cIt now competes with NVLink Fusion and UALink because they serve the same purpose, but the latter ones likely have better metrics and are more tailored to that use case,\u201d said Posner. \u201cHowever, PCIe is never going to go away. Intel uses it in its own architecture. We\u2019re just going to have to live with all these different protocols inside the die and outside the die.\u201d<\/p>\n Baya\u2019s Gayen agreed that multiple standards are here to stay. \u201cThere\u2019s an interesting tension in the industry today where hyperscalers are much more comfortable with Ethernet-based technologies. Because of that, Ultra Ethernet and the Open Compute Project\u2019s ESUN (Ethernet for Scale-Up Networking) initiatives have started up. They say, \u2018We\u2019re happy with Ethernet. We can keep going with that with just a few tweaks.\u2019 Then everybody is comfortable knowing these are the same lower-level stacks and infrastructure that they\u2019re familiar with. If your customers are happy with the technology, then that\u2019s a huge tailwind. UALink has more fundamental bones, built ground up for exactly what AI needs, whereas Ethernet has repeatedly won. This has happened in the past, as well, where Ethernet has evolved to meet needs, and so it\u2019s unclear what\u2019s going to win.\u201d<\/p>\n With scale-up and scale-out, and the plethora of protocols available, the challenge is deployment. \u201cSystems need to talk to each other, so there needs to be enough systems that speak the same protocol,\u201d said Cadence\u2019s Khan. \u201cThen, for these scale-up protocols to work, you need the switching infrastructure in between, so who\u2019s developing the switches for which one? That results in fragmentation. In some cases, SoC designers are having to put multiple solutions on their SoCs because they don\u2019t know what the market ecosystem will be like when systems are actually deployed.\u201d<\/p>\n ESUN-based switches already have the same Ethernet switch infrastructure. \u201cThey just have to update the protocol a bit, and then you have a new switch available, whereas if you\u2019re building something for a totally new protocol, it\u2019s a lot more work,\u201d said Khan. \u201cThere\u2019s some economics in terms of whether you want the change to be revolutionary or incremental. New protocols have both system implications and software programming implications. It is always challenging for new software to take advantage of the promised benefits of a new protocol.\u201d<\/p>\n Optical, CPO, and high-speed SerDes for the future \u201cWe are hearing more about optical interconnects, especially moving on to CPO (co-packaged optics),\u201d said Keysight\u2019s Lee. \u201cThis is changing the electrical interconnect to optical to overcome power issues. With AI chips, where a lot of ASICs are needed, the system configurations pull a lot of power, which is one of the main issues in AI data centers. Using CPO or silicon photonics will allow us to go lower power. You don\u2019t have to use ASICs in the system. Distance-wise, since you don\u2019t use copper, it saves you a lot of signal loss; therefore, the system is going to be much more effective, and also reduce thermal limits to the system.\u201d<\/p>\n Optical technologies are gaining traction because electrical links face a fundamental limit for how much bandwidth can be delivered through the limited chip-edge area. However, optical is still a niche option rather than default plumbing right now. \u201cOptical I\/O is creeping from \u2018research darling\u2019 toward selective deployment as packages get bandwidth-hungry and power-limited,\u201d said Arteris\u2019 Nightingale.<\/p>\n Conclusion: no clear winner \u201cStandardization is great if it works for everyone, but where standardization has an issue is that you have a lot of legacy infrastructure,\u201d said Cadence\u2019s Khan. \u201cIn a data center, if somebody comes up with a new standard \u2014 let\u2019s pick UALink as an example \u2014 for it to be successfully deployed, you now have to introduce all of these UALink switches for scale-up, and so on. It\u2019s a hefty lift in terms of expense. We saw that with CXL. The reason CXL adoption has been slow is that all the infrastructure required to actually deploy it is not in place. So designers ask, \u2018Can I achieve the same thing with a tradeoff on some amount of performance or latency with an existing solution?\u2019\u201d<\/p>\n The number of solutions to solve related problems is comparable to the EM (electromigration) technologies in the market 10-plus years ago. \u201cThere were so many different technologies, including FEM (finite element method), FTTD (finite difference time domain), MoM (method of moments), and far more,\u201d said Keysight\u2019s Hee-Soo. \u201cThe question was, why isn\u2019t there a single algorithm that solves all the different types of problems? They are all solving one thing, which is Maxwell\u2019s equation. But every technology has pros and cons. One may be really good at solving narrow-band problems, while the other is good at solving wide-band design problems. So, I don\u2019t think there will be only one interconnect standard that governs all different types of interfaces.\u201d<\/p>\n However, there are some clear losers. \u201cIn-memory systems, a pair of buses, single-ended, is very sensitive to noise issues,\u201d said Lee. \u201cIt also has many yield timing-related issues, and those are also very, very difficult. We are also hearing less about long-reach copper because it\u2019s very expensive with higher loss.\u201d<\/p>\n References<\/p>\n [1] All AI Data Center Interconnects Will Be Optical<\/a> Within 5 Years (Semiconductor Engineering)<\/p>\n [2] AI Optical Interconnect Boom<\/a> Drives U.S. Firms to Expand Southeast Asia Outsourcing, Opening the Door for Cross-Industry Entrants, Says TrendForce<\/p>\n Related Articles<\/p>\n Scale Up, Scale Out Get A New Partner<\/a> New Data Center Protocols Tackle AI<\/a> Optimizing Data Movement<\/a> Multiple AI Scale-Up Options Emerge<\/a>
Today\u2019s market is driven by chiplets and multi-die architectures, giving designers lower power and high bandwidth densities. A chiplet is an electrical die that is designed to do one function. Among emerging interconnects, there is an industry effort to reduce vendor lock-in through standardized chiplet interfaces such as UCIe or BoW.<\/p>\n![\"\"](\"https:\/\/www.newsbeep.com\/nz\/wp-content\/uploads\/2026\/05\/Screenshot-2026-05-17-at-12.16.56-PM.png\")
Fig. 1: Example of 3.5D packaging with a 3D die stack connected to another 2D die with an interposer and UCIe interface. Source<\/a>: Synopsys<\/p>\n
Many AI applications leverage traditional CXL PCIe links to enable disaggregated compute, so systems can dynamically share memory, storage, and accelerators across multiple compute nodes, according to<\/a> Rambus\u2019 Ternullo.<\/p>\n![\"\"](\"https:\/\/www.newsbeep.com\/nz\/wp-content\/uploads\/2026\/05\/Screenshot-2026-05-17-at-12.17.58-PM.png\")
Fig. 2: Examples of HPC chiplets using UCIe IP for die-to-die connectivity and PCIe 7 and CXL to connect CPU to memory. Source<\/a>: Synopsys<\/p>\n
The main competitors to Ethernet for high-speed GPU scale-up inside the rack are NVLink and UALink.<\/p>\n![\"\"](\"https:\/\/www.newsbeep.com\/nz\/wp-content\/uploads\/2026\/05\/Screenshot-2026-05-17-at-12.19.19-PM.png\")
Fig. 3: PCIe 7.0 switch IP with time division multiplexing. Source: Rambus<\/p>\n
Many AI data center interconnects are expected to be optical within about five years [1] and TrendForce predicts the global shipment volume of optical transceivers will triple from 26.5 million units in 2023 to more than 92 million units by 2026. [2]<\/p>\n
Every interconnect protocol has benefits and drawbacks, and there is no short answer for which I\/O and interconnect protocol is the best for a given application.<\/p>\n
For reaching farther into another data center, developers are now talking about scale-across.<\/p>\n
UALink scales up, while Ultra Ethernet scales out.<\/p>\n
Problems and solutions for improving performance with more data.<\/p>\n
As data center infrastructures adapt to evolving workloads, parts of Ethernet can be found in scale-up approaches.<\/p>\n