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L-R: D2S\u2019 Fujimura; Micron\u2019s Scheid; HJL\u2019s Levinson; and Synopsys\u2019 Fenger<\/p>\n
SE: What do you see today as the biggest technical bottleneck in mask technology? Is it throughput, inspection limits, or something else?<\/p>\n
Levinson: If you talk about bottlenecks in terms of time, when you have a design and you want to get a mask out, the item that we\u2019ve been dealing with at every node is mask defect inspection and repair. It\u2019s a lengthy cycle \u2014 doing the inspection, confirming you have defects, repairing the defects, confirming the repairs, and so forth. That takes a long time. Mask writing used to be a big part of the problem, but with multi-beam mask writers, that\u2019s gotten quite a bit better. But mask defect inspection remains the biggest technical bottleneck.<\/p>\n
Fujimura: Dealing with the data is also a big part of it. The move to curvilinear is bringing some data volume issues. We\u2019re in an era where my phone has 1TB of storage, so I don\u2019t perceive it as a huge barrier. But I do notice that the industry is seeing it as a big barrier. It\u2019s worse than it was before. With curvy, you need more data to represent all the shapes of a design. Mask shops have to archive their designs, so there\u2019s a multiplier there, too. Storage, transmission, reading, and writing all have an impact. I don\u2019t think it\u2019s prohibitively long, but it\u2019s something everybody has to adjust to. If this were the 1980s or \u201990s or even 2000s, it would have been impossible. The computing infrastructure just could not handle it. We can handle 5 TB files now. But everybody has to make adjustments.<\/p>\n
Scheid: Total turn time of leading-edge masks \u2014 specifically EUV masks \u2014 takes longer. If these masks are late to deliver, they can severely bottleneck the end product. Computation time for mask data prep is driven by data volume. It\u2019s possible to improve speed with even higher core counts and more efficient processing, but add in full chip curvilinear and the data could easily become the bottleneck. In addition, on the defect cycle Harry referenced in manufacturing, there\u2019s the extra element of needing to carefully prepare the blank to make sure all defect locations are known, characterized, and can be avoided, so we aren\u2019t dealing with non-repairable defects after processing. There\u2019s a lot more upfront work, both on data and on physical material preparation before an EUV order can even begin, and throughput bottlenecks have to be carefully managed.<\/p>\n
Fenger: At the leading edge, the bottleneck in EUV really isn\u2019t a single tool. It\u2019s an iteration loop across compute, mask, and wafer correlation to yield. Along the same lines, inspection of masks is becoming a bottleneck for mask throughput. What\u2019s really needed now is not just detectability, but printability, correlating inspection results to actual wafer yield and wafer defects, and to sift through the huge number of defects being detected and determine which ones matter.<\/p>\n
SE: Mask data volumes and pattern complexity have exploded with curvilinear ILT and advanced OPC. Are we approaching practical limits in mask data preparation and writing? And how is the industry adapting to the scale of complexity, especially with curvilinear masks?<\/p>\n
Fujimura: No, I don\u2019t think we are at the limit. Compared to many other things that have to be done in the world, the amount of data required is really not prohibitive. It does cost more than before, but I don\u2019t think it\u2019s prohibitive. It\u2019s just that the industry has to be convinced that it\u2019s necessary, and that curvilinear has enough benefits that it\u2019s the right thing to do, and it has to be able to get the approvals to build the infrastructure. I think it will happen. It\u2019s just that it is a barrier today with infrastructure that was built for masks made ten years ago.<\/p>\n
Scheid: It\u2019s important to look at what the capability is of software to produce curvilinear patterns and compare that to the reality in manufacturing. I would describe what we\u2019ve been seeing as less of an explosion and more of a controlled expansion of data size. In manufacturing today, the application of curvilinear patterning is targeted. Particularly complex areas of patterns have the most value in using a curvilinear or ILT solution. When combining that with good fracture practices, including piecewise approximations, we can get most of the value while keeping file sizes under control. One example of the industry adapting to complexity is leveraging scalable compute. It enables capability to handle larger file sizes without adding a large on-prem footprint.<\/p>\n
Fenger: I agree with Aki. We\u2019re not really hitting a limit on data size. We\u2019re hitting a limit on turnaround time. We have to look at how fast we can get the mask out the door, given the complexity of what we\u2019re being asked to write. This is why we are pursuing GPU-accelerated compute such as ILT and OPC. The consideration of fracture time needs to be part of the OPC exercise, meaning we need some understanding of what choices we make in our ILT or OPC that are going to impact downstream flows in terms of generating the mask in a short cycle time \u2013 perhaps even removing the need for fracture. The complexity has really moved from polygons to intent. Glenn just mentioned they change polygons to make fracture more friendly, removing unnecessary fracture points. We need to understand what we really want to get out of manufacturing the mask and what changes we can make upstream to get the benefit without the added overhead.<\/p>\n
Levinson: It\u2019s always been a challenge, and it just continues to be, because every node means more data and higher demands for turnaround. The bar just keeps getting raised. The good news is that there\u2019s a lot of investment in artificial intelligence, with enormous resources going into how to handle large data volumes and very big computations. We benefit from all these other people driving that, and of course, we help ourselves by creating the new technology that then allows us to do more things. It used to be a kind of joke for us many years ago, where we\u2019d come up with test chips for a new generation of technology, and the first thing we would do is crash all the computers being used for generating the masks, because it was the first time everybody was trying to make something with that amount of data. We would laugh today at the amount of data we were talking about then. We measured things in megabytes, then gigabytes, and now terabytes. But as I said, the bar just keeps getting raised.<\/p>\n
SE: Curvilinear masks are becoming more common at the leading edge, with production data emerging. What are the results telling us about the current and future state of mask technology? Is curvilinear becoming more viable, and does it provide options that haven\u2019t existed before?<\/p>\n
Scheid: Results are telling us curvilinear is here to stay. The mask ecosystem is preparing for the increased complexity, and we see that through the papers addressing the topic at BACUS. Industry volumes are still relatively low, but it does enable enhanced image fidelity and process robustness on the most challenging patterns. Mask shops are able to produce these masks with current mask-making technology. But we are starting to see more sophisticated metrology requirements, like edge placement error, as increasingly necessary to validate the quality and consistency of patterning. Bottom line is that curvilinear has become viable. It\u2019s here, and I expect we will continue to see more of it, eventually driving back even further in the chain, all the way to design.<\/p>\n
Fenger: It\u2019s been demonstrated that curvilinear brings value in terms of wafer performance, but it\u2019s very design-specific and layer-specific. I see curvilinear becoming an available option that will be used where it makes sense, and I don\u2019t think it\u2019ll be general usage on every layer. That being said, with the wide adoption of MBW, there could be a day when there is cost parity between Manhattan and curvilinear masks, and in that scenario we would always choose curvilinear. The real challenge I see with curvilinear is qualification. We can print it, but can we manufacture it, qualify it, and do it predictably at scale? There are still some gaps in terms of how to qualify a curvilinear mask. Multiple mask shops have different requirements and different specifications. They\u2019re looking at the mask in different ways. There seems to be a lack of agreement between peer mask shops in terms of how a curvilinear mask is qualified. We may need to come up with a standard.<\/p>\n
Levinson: It definitely brings great benefits. A couple of decades ago, when people first started looking at inverse lithography technology, we saw that getting curvy features on the masks brought benefits. Now we see that actually putting curvilinear into what you\u2019re targeting on the wafer has a lot of benefits. We\u2019ve woken up to that fact and are addressing all the technical challenges needed to build it into the process flow. I edit the Journal of Micro\/Nanopatterning, Materials, and Metrology, and we currently have an open call for papers for submissions on metrology for curvilinear features. It\u2019s very much a topic of active R&D. We\u2019re making progress, but you have to get through all of this before we\u2019re ready to just take our designs, run them through, and out comes a curvilinear mask. We\u2019re right in the middle of it.<\/p>\n
Fujimura: There are industry efforts to improve the data sizes, with the SEMI P49 standard and things like that. The industry is acting on this. I think of curvilinear more in terms of what we mean by \u2018manufacturable.\u2019 There are many curvilinear patterns that are not manufacturable. What we know is that 90-degree corners are not manufacturable. Being able to specify only shapes that are expected to be manufacturable on a mask is key to taking advantage of curvilinear. For every non-precision layer, corner rounding continues to not matter. But for layers that require accuracy, the critical layers, I do think they should go all curvilinear, even if it\u2019s just line-and-space patterns. The line ends should be corner-rounded before you give them to the mask to manufacture, because you know they\u2019re going to end up being corner-rounded anyway. If you specify a manufacturable shape, it will not only be manufactured to that shape if you have proper MPC, but it will also be more reliably manufacturable. Dose margin, which is the proxy for mask variation, is always worse for areas of the mask shapes that are not manufacturable. Manufacturable shapes always have better dose margin. If you want to create a mask where variation is limited, you should target manufacturable shapes. I keep saying, \u2018Ask for what you can get, and get what you ask for.\u2019 ILT programs should be band-limited so that they\u2019re only asking for shapes that can be manufactured on a mask, and then the mask shop\u2019s job is to create that exactly and more consistently every time.<\/p>\n
That helps inspection, too, because now you have fewer nuisance defects. You\u2019re not looking for corners that are sometimes rounded by 12 nanometers and sometimes by 14, and you can\u2019t tell if it was just a normal rounding error or a real defect. You don\u2019t have that issue if you\u2019re asking for manufacturable shapes, so inspection becomes easier. Metrology is definitely an issue. The eBeam Initiative survey \u2014 an annual survey of luminaries in the field \u2014 clearly shows that the industry now perceives the number-one and number-two issues are data infrastructure and ILT (that produces the data). But the number-three issue, as a potential barrier to curvilinear, is metrology. The world is used to doing one-dimensional critical dimension measurements. You take multiple scan lines across the CD of parallel lines, average them, and get accuracy out of the act of averaging. How to do the same thing when you have curvilinear shapes is something a number of papers address. Micron has published some papers on this. It\u2019s being actively worked on, but it\u2019s not a settled issue yet.<\/p>\n
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