AMD today announced the 6th Gen EPYC “Venice” server processors powered by the “Zen 6” CPU microarchitecture. The family includes a set of four distinct product lines, the EPYC 9006 (Socket SP7) for mainline servers with market leadership in core-counts and performance; the EPYC 9006 (Socket SP8) for enterprises with optimized performance per node; EPYC 9006X SP7 for high performance computing accelerated by larger CPU caches; and the EPYC 9006 LP “Verano” processors for AI host nodes powered by LPDDR memory.

The EPYC 9006 “Venice” family offers CPU core counts of up to 96-core/192-thread on chips with “Zen 6” cores, and up to 256-core/512-thread on chips with compacted “Zen 6c” cores. “Venice-X” HPC processors with 3D V-Cache offer up to 1,152 MB of L3 cache per socket. AMD has significantly upgraded the memory sub-system of these processors, giving Socket SP7 a 16-channel DDR5 memory interface with native support for DDR5-8000 RDIMMs, support for MRDIMMs with up to DDR5-12800 speeds. Specific variants also come with 24-channel LPDDR5X interfaces that support field-replaceable SOCAMM2 modules.

In terms of platform, EPYC “Venice” supports 1P and 2P socket configurations. Each socket puts out 128 PCI-Express Gen 6 lanes, with support for memory expansion via CXL 3.1 and 5th Gen Infinity Fabric. The company introduced several new power-management and QoS features for admins, including support for unified power provisioning (UPP), utilization-based power scaling (UBPS), and FAST (frequency-adaptive spectrum technology). AMD also introduced several new security features, both at the “Zen 6” microarchitecture-level, and specific to its server processors at the sIOD-level. These include enhanced RoT and RSA 4K encryption with PQC support; and mitigations for several new kinds of physical and side-channel attacks.AMD EPYC “Venice” series is in production now, with the 9006 SP7 series shipping in Q4 2026, 9006 SP8 bound for the first half of 2027, the 9006X SP7 series HPC processors bound for the second half of 2027, along with the 9006 LP series.Riding on IPC improvements of the “Zen 6” cores, wider 16-channel DDR5 memory interfaces, and faster DDR5-8000 memory, EPYC processors are shown offering significantly higher throughput and performance against contemporaries from Intel and Arm.

Performance Claims

AMD frames Venice as extending five generations of EPYC leadership, quoting up to 18x the throughput of its 1st Gen “Naples” EPYC 7601. Against the competition (all AMD-measured or -estimated):vs. NVIDIA Vera (88C): Up to 2.2x the throughput on SPECrate 2026_int_base (256C/600 W), 1.2x higher per-core performance (96C HF), and up to 2.8x agents per watt. AMD also claims a “Venice”-powered rack delivers up to 2.2x the cores of a Vera-powered rack.vs. Intel Xeon 6980P (128C): Up to 1.3x higher per-core performance and up to 3.3x performance in sandbox scenarios.vs. Arm AGI (136C): Up to 2.0x the throughput on SPECrate 2017_int_base.Cloud-native: Up to 2.6x-3.7x on MongoDB, Redis, NGINX and MySQL versus 6th Gen Intel Xeon.HPC: Up to 3.1x on GROMACS, NAMD, Quantum Espresso and WRF.Host node: 1.8x higher tokens/s for frontier models versus 5th Gen EPYC “Turin,” thanks to PCIe Gen 6 doubling CPU-to-GPU bandwidth.Consolidation: AMD claims 1000 aging 2P Intel Xeon Gold 6258R servers can be replaced by just 82 2P EPYC 9996 servers—up to 92% fewer servers, up to 77% less power, and up to 40% lower 5-year TCO.The complete slide-deck follows.