<\/p>\n What he did describe was 14nm logic bonded directly to 18nm DRAM to drastically increase memory bandwidth and reduce compute latency. He said the system’s power efficiency reaches 2 TFLOPS per watt, with a claimed total throughput of 120 TFLOPS, which is much higher than Nvidia\u2019s A100 GPUs. He argued that by placing memory and logic in the same package, the chip avoids the \u201cmemory wall\u201d that hinders large-scale GPU deployments.<\/p>\n Best picks for you<\/p>\n Wei added that the chip is part of a fully domestic supply chain effort and will be formally disclosed in detail later this year. The ultimate goal, he said, is to sidestep Western supply chain constraints, cut costs, and decouple China\u2019s AI development from U.S. vendors at both the hardware and software levels.<\/p>\n Memory wall and node stagnation<\/p>\n Wei’s comments put forward a direct challenge to the dominant logic of semiconductor development over the last decade. Where U.S. and Taiwanese chipmakers have focused on smaller transistors \u2014 Apple’s M3 at 3nm<\/a> and Nvidia\u2019s Hopper at 4nm<\/a> \u2014 China\u2019s researchers are now pitching advanced packaging and system architecture as a way to restore competitiveness using older manufacturing nodes.<\/p>\n The architecture described involves stacking a logic chip built on a 14nm process directly onto or alongside 18nm DRAM, using 3D hybrid bonding. This technique differs from traditional package-on-package or chiplet interconnects, in that it allows extremely dense, low-latency, high-bandwidth connections between dies. Unlike wire bonding or organic interposers, hybrid bonding directly fuses copper-to-copper contacts between wafers or die surfaces at the micron scale, supporting much higher interconnect density and thermal performance.<\/p>\n \n (Image credit: Nvidia)<\/p>\n According to Wei, this layout enables near-memory compute, with logic operations executed in close proximity to memory blocks. That reduces the energy and latency cost of frequent memory fetches, often the limiting factor in AI workloads. He said software-defined logic further boosts efficiency by allowing compute units to be dynamically mapped and configured for AI-specific workloads.<\/p>\n He also suggested that a theoretical performance of 120 TFLOPS could be reached with a total power draw of 2 TFLOPS per watt, which would place the architecture well above the energy efficiency of Nvidia\u2019s A100 and in the territory of Hopper-class or Blackwell-class chips<\/a>. It also implies a significant advantage over CPU-bound systems like Intel Xeon, which Wei said remain less efficient for large model training.<\/p>\n He stopped short of naming which Chinese firms are building silicon around this model, but past Chinese state media coverage has identified national champions such as Cambricon, Loongson, and Biren as players developing GPGPU-class accelerators. Cambricon in particular has previously discussed near-memory architectures and filed patents related to logic-in-memory compute.<\/p>\n CUDA dependency \u2018traps\u2019<\/p>\n Wei devoted a significant part of his address to outlining how he sees the entrenchment of CUDA as a vulnerability in the global AI industry. He argued that the early compatibility between large AI models and Nvidia\u2019s GPGPU architecture created a cycle of increasing architectural dependency. Over time, software was designed for CUDA and Nvidia optimized its hardware for deep learning workloads, leading to what Wei called a “deep pit” of mutual dependence between model developers and GPU vendors.<\/p>\n Don’t miss these<\/p>\n He claimed that this dynamic leaves alternative architectures \u2014 such as domestic AI chips incompatible with CUDA \u2014 with almost no route to widespread adoption, regardless of theoretical performance. In his view, if China becomes similarly locked into this ecosystem, it will effectively lose sovereignty over its AI<\/a> trajectory.<\/p>\n \n (Image credit: Nvidia)<\/p>\n Wei is clearly not alone in this line of thought. Chinese companies such as Cambricon and Huawei have advanced CUDA alternatives and software abstraction layers in parallel with domestic AI hardware, with state-aligned investment efforts backing broader ecosystem development. Cambricon\u2019s NeuWare stack, for instance, now offers compatibility with PyTorch, TensorFlow, and ONNX, and provides migration tools for CUDA-trained models. Alibaba and Huawei have similarly promoted their own developer frameworks targeting Ascend and XuanTie hardware.<\/p>\n Wei warned that continued reliance on U.S.-controlled software and toolchains would carry \u201cvery serious\u201d consequences, both economically and geopolitically. He said China\u2019s goal is to \u201cabandon U.S. technology routes\u201d and build a domestic AI technology stack that is resilient to supply chain shocks and regulatory constraints.<\/p>\n The Chinese are right to be concerned. In recent years, the U.S. has significantly expanded its export controls and blocked Nvidia from selling its leading hardware to Chinese firms. In response, the company introduced modified, lower-performance chips<\/a>, which were also eventually restricted. Today, now that Nvidia has no market share left in China<\/a>, domestic companies rely on legacy hardware or workarounds using second-tier accelerators and the grey market.<\/p>\n Not yet proven<\/p>\n The claims made at ICC raise questions that cannot yet be answered without detailed benchmarks<\/a> and independent testing. While hybrid bonding<\/a> is an established technology, the real-world performance of a full stack built on 14nm logic and 18nm DRAM remains to be seen.<\/p>\n Thermal dissipation in 3D stacks is still a major concern, particularly when logic and memory are in close proximity, and airflow is limited. Hybrid bonding also requires very high manufacturing precision and wafer alignment. These challenges could impact both yield and cost. China\u2019s domestic foundries, including SMIC, are known to have strong 14nm-class production lines, but hybrid bonding at scale for logic-memory stacks would be a new capability.<\/p>\n Breaking Nvidia\u2019s lock on the model training ecosystem<\/a> also requires not just raw performance parity, but broad software support and capable developers. Even if China succeeds in building a functionally equivalent AI processor, adoption will remain limited without tooling and integration into PyTorch or TensorFlow workflows.<\/p>\n Still, with EUV lithography out of reach and GAA transistor designs still years away for domestic fabs, architectural innovation and packaging integration may be China\u2019s most viable path to short-term competitiveness in high-performance AI workloads. Wei indicated that more technical details would be shared in future disclosures, but did not confirm whether working silicon had been produced.<\/p>\n Follow Tom’s Hardware on Google News<\/a>, or add us as a preferred source<\/a>, to get our latest news, analysis, & reviews in your feeds.<\/p>\n![\"Nvidia\"](\"https:\/\/www.newsbeep.com\/uk\/wp-content\/uploads\/2025\/11\/z53fPgXjpKHTpeGv3RHpqj.png\")
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