{"id":123541,"date":"2025-08-31T21:54:08","date_gmt":"2025-08-31T21:54:08","guid":{"rendered":"https:\/\/www.newsbeep.com\/us\/123541\/"},"modified":"2025-08-31T21:54:08","modified_gmt":"2025-08-31T21:54:08","slug":"intel-plans-virtual-super-processor-cores","status":"publish","type":"post","link":"https:\/\/www.newsbeep.com\/us\/123541\/","title":{"rendered":"Intel plans virtual &#8220;super processor cores&#8221;"},"content":{"rendered":"<p>              Intel plans virtual &#8220;super processor cores&#8221;<\/p>\n<p>Intel has applied for patents for &#8220;software-defined supercores&#8221; (SDC) in several countries. This involves several slim CPU cores cooperating for higher single-threading performance when required. This is apparently intended to solve a well-known dilemma for CPU developers: For maximum single-threaded performance, a CPU core needs as many computing units that can be used in parallel as possible. However, such a &#8220;wide&#8221; core takes up a lot of silicon space and draws a lot of power at high clock frequencies. For high multi-threaded computing performance, on the other hand, many compact cores can be more favorable.<\/p>\n<p>Familiar idea, newly implemented<\/p>\n<p>The idea of using several compact computing units in parallel if required has already been implemented. In Zen cores up to the Zen 4 generation, AMD connects two AVX2 computing units, each 256 bits wide, in order to process AVX 512 instructions.<\/p>\n<p>A more general concept is the <a href=\"https:\/\/www.heise.de\/news\/Bit-Rauschen-Die-Intel-Chipfabrik-in-Magdeburg-steht-auf-der-Kippe-9881917.html?from-en=1\" rel=\"nofollow noopener\" target=\"_blank\">Coarse-Grain Reconfigurable Array (CGRA)<\/a>, which interconnects a certain number of small execution units depending on the computing task.<\/p>\n<p>Conversely, there have also been processors in which two cores share certain computing units, such as the <a href=\"https:\/\/www.heise.de\/news\/AMD-Details-der-2011-kommenden-Prozessorkerne-Bobcat-und-Bulldozer-857374.html?from-en=1\" rel=\"nofollow noopener\" target=\"_blank\">AMD Bulldozer architecture with &#8220;Shared FPU&#8221;<\/a>.<\/p>\n<p>SDC details<\/p>\n<p>      <a href=\"https:\/\/www.heise.de\/imgs\/18\/4\/9\/2\/7\/8\/6\/4\/SDC-3-e9e189617193ecd8.png\" rel=\"nofollow noopener\" target=\"_blank\"><\/p>\n<p>  <img loading=\"lazy\" decoding=\"async\" alt=\"Software-defined supercores: two cores share the workload\" height=\"877\" src=\"data:image\/svg+xml,%3Csvg xmlns='http:\/\/www.w3.org\/2000\/svg' width='696px' height='391px' viewBox='0 0 696 391'%3E%3Crect x='0' y='0' width='696' height='391' fill='%23f2f2f2'%3E%3C\/rect%3E%3C\/svg%3E\" style=\"aspect-ratio: 1200 \/ 877; object-fit: cover;\" width=\"1200\"\/><\/p>\n<p>      <\/a><\/p>\n<p>Software-defined supercores: two cores share the workload<\/p>\n<p class=\"a-caption__source\">\n      (Image:\u00a0Intel, US-Patentanmeldung US20250217157A1, Google)\n    <\/p>\n<p>In <a href=\"https:\/\/patents.google.com\/patent\/US20250217157A1\/en\" rel=\"external noopener nofollow\" target=\"_blank\">patent application US20250217157A1<\/a>, Intel explains the functionality of a software-defined supercore in more detail. For example, two cores could work together as an SDC to process a single thread faster. Flow control instructions in the code provide information on which code sections should be processed in parallel if possible.<\/p>\n<p>According to the patent application, relatively little additional hardware is required in each core for this cooperation to work efficiently.<\/p>\n<p>Solution to the P-core problem?<\/p>\n<p>If you compare current x86 processors from AMD and Intel, you will notice that Intel&#8217;s performance (P) cores take up a relatively large amount of space. Intel&#8217;s efficiency cores (E-cores) are much more compact, with an area ratio of almost four to one. With single-threading, however, the E-cores are significantly weaker than the P-cores. Dynamically combinable, slimmer cores could provide a remedy.<\/p>\n<p>AMD has so far not used E-cores in this sense, but more compact and efficient Zen cores with the same range of functions (Zen 5\/5c).<\/p>\n<p>AMD and Intel are planning several innovations to the x86 architecture. They joined forces in fall 2024 to form the <a href=\"https:\/\/www.heise.de\/news\/AMD-und-Intel-verbuenden-sich-gegen-ARM-9982449.html?from-en=1\" rel=\"nofollow noopener\" target=\"_blank\">x86 Ecosystem Advisory Group (EAG)<\/a>. According to a post by AMD Vice President Robert Hormuth on LinkedIn, the x86 partners have agreed on FRED, AVX10 and APX, among other things.<\/p>\n<p><a href=\"https:\/\/www.heise.de\/news\/Bit-Rauschen-Intels-RISC-V-Liebe-Bugs-Interrupts-und-IBM-vs-Globalfoundries-6120354.html?from-en=1\" rel=\"nofollow noopener\" target=\"_blank\">Flexible Return and Event Delivery (FRED)<\/a> is an updated concept for processing interrupts. <a href=\"https:\/\/www.heise.de\/news\/Intel-APX-Effizienter-und-schneller-mit-neuer-x86-Befehlssatzerweiterung-AVX10-9225901.html?from-en=1\" rel=\"nofollow noopener\" target=\"_blank\">AVX10 and the Advanced Performance Extensions (APX)<\/a> reorganize the AVX versions and bring, among other things, twice as many registers. <a class=\"heiseplus-lnk\" href=\"https:\/\/www.heise.de\/news\/Bit-Rauschen-Intels-uebernaechste-Desktop-CPU-soll-ein-Kracher-werden-10368244.html?from-en=1\" rel=\"nofollow noopener\" target=\"_blank\">Intel&#8217;s Nova Lake<\/a>, which is expected to arrive at the end of 2026 as the Core Ultra 400 for LGA1954 boards, could be the first Intel CPU with APX and AVX10.2.<\/p>\n<p>(<a class=\"redakteurskuerzel__link\" href=\"https:\/\/www.heise.de\/en\/news\/mailto:ciw@ct.de\" title=\"Christof Windeck\" rel=\"nofollow noopener\" target=\"_blank\">ciw<\/a>)<\/p>\n<p class=\"a-u-mb-1\">\n      Don&#8217;t miss any news \u2013 follow us on<br \/>\n      <a class=\"a-u-inline-link\" href=\"https:\/\/www.facebook.com\/heiseonlineEnglish\" rel=\"nofollow noopener\" target=\"_blank\">Facebook<\/a>,<br \/>\n      <a class=\"a-u-inline-link\" href=\"https:\/\/www.linkedin.com\/company\/104691972\" rel=\"nofollow noopener\" target=\"_blank\">LinkedIn<\/a> or<br \/>\n      <a class=\"a-u-inline-link\" href=\"https:\/\/social.heise.de\/@heiseonlineenglish\" rel=\"nofollow noopener\" target=\"_blank\">Mastodon<\/a>.\n    <\/p>\n<p class=\"a-u-mb-0\">\n      This article was originally published in<\/p>\n<p>        <a class=\"a-u-inline-link\" href=\"https:\/\/www.heise.de\/news\/Intel-plant-virtuelle-Super-Prozessorkerne-10626845.html\" rel=\"nofollow noopener\" target=\"_blank\">German<\/a>.<\/p>\n<p>      It was translated with technical assistance and editorially reviewed before publication.\n    <\/p>\n<p>\n      Dieser Link ist leider nicht mehr g\u00fcltig.\n    <\/p>\n<p>Links zu verschenkten Artikeln werden ung\u00fcltig,<br \/>\n      wenn diese \u00e4lter als 7\u00a0Tage sind oder zu oft aufgerufen wurden.\n    <\/p>\n<p>Sie ben\u00f6tigen ein heise+ Paket, um diesen Artikel zu lesen. Jetzt eine Woche unverbindlich testen \u2013 ohne Verpflichtung!<\/p>\n","protected":false},"excerpt":{"rendered":"Intel plans virtual &#8220;super processor cores&#8221; Intel has applied for patents for &#8220;software-defined supercores&#8221; (SDC) in several countries.&hellip;\n","protected":false},"author":2,"featured_media":123542,"comment_status":"","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[46],"tags":[191,4115,2852,79072,74],"class_list":{"0":"post-123541","1":"post","2":"type-post","3":"status-publish","4":"format-standard","5":"has-post-thumbnail","7":"category-computing","8":"tag-computing","9":"tag-intel","10":"tag-it","11":"tag-prozessoren","12":"tag-technology"},"_links":{"self":[{"href":"https:\/\/www.newsbeep.com\/us\/wp-json\/wp\/v2\/posts\/123541","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.newsbeep.com\/us\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.newsbeep.com\/us\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.newsbeep.com\/us\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/www.newsbeep.com\/us\/wp-json\/wp\/v2\/comments?post=123541"}],"version-history":[{"count":0,"href":"https:\/\/www.newsbeep.com\/us\/wp-json\/wp\/v2\/posts\/123541\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.newsbeep.com\/us\/wp-json\/wp\/v2\/media\/123542"}],"wp:attachment":[{"href":"https:\/\/www.newsbeep.com\/us\/wp-json\/wp\/v2\/media?parent=123541"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.newsbeep.com\/us\/wp-json\/wp\/v2\/categories?post=123541"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.newsbeep.com\/us\/wp-json\/wp\/v2\/tags?post=123541"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}