Now, new details have been shared that provide more insight into ZAM memory. For starters, the new memory is set to offer 2x the bandwidth as HBM4, even rivaling the next-generation HBM4E standard, which isn’t expected till next year. ZAM itself is aiming at a 2028-2030 timeframe, so it will be some time before the project hits production level.<\/p>\n
At VLSI Symposium 2026, Intel and SoftBank subsidiary, SAIMEMORY<\/a>, will unveil new details and have already previewed some features of the upcoming standard. The new details have highlighted various aspects that we will discuss in detail.<\/p>\n Starting with the design itself, ZAM or Z-Angle memory is being demoed with a 9-layer stacked design. A single stack includes eight DRAM stacks, each with a 3 micron silicon substrate between each stack. The main substrate features a single Logic controller that supplements all nine DRAM stacks.<\/p>\n There are three main TSV layers, with each layer packing 13.7k Through-Silicon-Vias inter-connect paths that utilize hybrid bonding. Each layer offers 1.125 GB per layer, so we are looking at a 10 GB capacity per stack or 30 GB in the entire package. The ZAM stack measures 171mm2 (15.4 x 11.1mm), and the memory offers 0.25 Tb\/s bandwidth per mm2 equaling 5.3 TB\/s of bandwidth per stack.<\/p>\n Now let’s talk about the advantages of HBM memory. Currently, HBM is the preferred choice for high-performance AI accelerators and GPUs. But as HBM scales up, it also leads to structural problems, including more heat and higher power. ZAM addresses three core areas: high-density, wide-bandwidth, and lower power consumption. ZAM’s structural characteristics allow for a vertical build that is great for heat dissipation without the need to pass through the wiring layer.<\/p>\n Key Advantages of ZAM:<\/p>\n Higher Bandwidth Density: ~0.25 Tb\/s\/mm\u00b2 (vs. lower in HBM)<\/p>\n Lower Power Consumption: Optimized for low data transfer power<\/p>\n Superior Heat Dissipation: Vertical architecture allows better thermal management (HBM suffers from heat buildup due to wiring layers)<\/p>\n Ultra-High Stacking: Supports 9+ layers with extremely thin 3\u03bcm Si per stack and via-in-one TSV<\/p>\n Innovative Tech: Magnetic field coupled wireless I\/O + advanced bonding for scalability<\/p>\n AI-Optimized: Addresses HBM’s structural limits for generative AI workloads<\/p>\n The final goal with ZAM is to achieve a dense 3D memory design through 3.5D packaging technology, which houses vertical and horizontal layers, including the high-bandwidth, large memory stack, Power\/Ground rails, Silicon Photonics, and Legacy IO, all on a single substrate. ZAM sure does sound very promising, and we look forward to the first real-time demo, but for it to be recognized as a truly competitive solution against HBM, it needs to see real application, and what better way to do so speedily when the AI markets are going in full force.<\/p>\n News Sources: OGAWA Tadashi <\/a>, Alex<\/a><\/p>\n \t\t\t\t\t\t\t\t\t \n\t\t\t\t\tAbout the author<\/a>: A Software Engineer by training and a PC enthusiast by passion, Hassan Mujtaba serves as Wccftech’s Senior Editor for hardware<\/a> section. With years of experience in the industry, he specializes in deep-dive technical analysis of next-generation CPU and GPU architectures, motherboards, and cooling solutions. His work involves not only breaking news on upcoming technologies but also extensive hands-on reviews and benchmarking.\t\t\t\t<\/p>\n![\"A](\"https:\/\/www.newsbeep.com\/us\/wp-content\/uploads\/2026\/05\/Z-Angle-Memory-ZAM-from-Intel-scaled.jpg\")
<\/a><\/p>\n![\"A](\"https:\/\/www.newsbeep.com\/us\/wp-content\/uploads\/2026\/05\/Intel-ZAM-Z-Angle-Memory-vs-HBM.jpg\")
<\/a><\/p>\n
\n\t\t\t\t\t\t![\"Hassan](\"https:\/\/www.newsbeep.com\/us\/wp-content\/uploads\/2026\/05\/Hassan.jpg\")
\n\t\t\t\t\t<\/a><\/p>\n