The semiconductor industry’s shift toward chiplet-based architectures has created significant mixed-signal verification challenges for high-speed die-to-die interconnects. Traditional verification approaches force difficult trade-offs: Digital mixed-signal (DMS) flows sacrifice analog fidelity, while Analog mixed-signal (AMS) flows struggle with scalability and manual overhead. This paper details how AnalogPort, a leading high-speed interconnect solutions provider, successfully addressed these limitations using Siemens EDA’s Symphony Pro (part of Solido Simulation Suite) for their complex 32 Gbps, 16-transmit/16-receive full-duplex interface. Symphony Pro enabled AnalogPort to deploy UVM methodology while seamlessly combining high-fidelity SPICE simulation for critical analog blocks with high-performance digital simulation for the broader system. By extending their UVM-based digital verification into the mixed-signal domain, AnalogPort achieved a standardized, scalable flow that delivered both analog accuracy and simulation performance, successfully meeting strict project timelines.
Introduction
The semiconductor industry is undergoing a fundamental shift toward chiplet-based architectures and die-to-die interconnect solutions. This transition is driven by multiple converging factors: the exponential growth of artificial intelligence (AI) and machine learning workloads demanding massive data throughput, the complexity of integrating diverse functional blocks (processors, memory, analog circuits, radio frequency (RF) components) on a single die, and the economic pressures of manufacturing at advanced process nodes.
Traditional monolithic system-on-chip (SoC) designs are increasingly unable to meet the performance, power efficiency, and thermal management requirements of applications spanning data centers, automotive systems, mobile devices, and edge computing. The technical and economic constraints of single-die integration have created an urgent need for alternative architectures.
To address these challenges, semiconductor leaders have adopted innovative approaches including high-bandwidth memory (HBM), specialized processor architectures, optical interconnects, and advanced packaging techniques. Chiplet-based disaggregation of SoCs, enabled by efficient die-to-die interconnect technologies has emerged as a particularly promising solution. This modular approach allows companies to combine specialized chiplets optimized for different functions and process technologies, accelerating time-to-market while improving yield, cost, and performance across diverse applications. High-speed interconnects are a critical component of chiplet-based SoC architectures.